The present invention relates generally to reliability assessment for semiconductors, and more specifically, to dielectric reliability assessment for advanced semiconductors.
Recently, low-K dielectrics have been introduced into advanced semiconductor technologies to improve performance by reducing time-delay, noise and power dissipation. As a result of scaling of interconnect pitch, an increase in process complexities and geometric variabilities such as dielectric spacing variations, via misalignment, accurate reliability assessment of time-dependent dielectric breakdown (TDDB) has become difficult.
In contrast to traditional dielectrics, the TDDB distributions of low-K dielectrics do not always have a Weibull distribution and do not follow Poisson area scaling. In some cases, the TDDB data at very high cumulative failure percentiles do not show significant area-sensitivity. However, at low cumulative failure percentiles, the TDDB data tends to merge into a universal distribution after applying Poisson area scaling. These delirious effects have become so severe that it becomes impossible to accurately extract the time-scale and slope parameters.
Currently, in an effort to overcome these difficulties, sophisticated modeling schemes have been developed. These modeling schemes are time consuming to develop and often involve the use of several parameters. For example, in the case of variation of dielectric thickness, or spacing, a convolution-based modeling approach requires a minimum of six parameters. In most cases, the experimental work that is required to derive these sophisticated models is extremely time consuming and expensive. In addition, the methodology currently used for modeling dielectric reliability in traditional CMOS technologies is often too conservative when applied to advanced CMOS technologies, which may result in wasted time and money designing circuits attempting to satisfy this overly conservative projection.